Pre-route Design Flow for Multi-Gigabit SerDes Channels-webinar
March 19, 2020 @ 8:00 am - 5:00 pm
“Designing today’s multi-gigabit SerDes channels is challenging. Careful consideration must be given to discontinuities in the channel to ensure reliable and robust product operation.
In this webinar, we will show you how to evaluate tradeoffs and derive constraints early in the design cycle, using HyperLynx GHz pre-layout simulation to optimize critical areas and assess their impact on overall channel performance. These areas include BGA break-outs, DC blocking capacitors and connector pins, which must be as electrically transparent as possible to maximize channel operating margins.
What you will learn:
How to run Channel Operating Margin (COM) analysis on serial channels
How HyperLynx progressive analysis allows you to isolate and assess the impact of different physical effects on channel margin
How to create and optimize critical areas using the 3D full-wave solver
How to use swept parameter analysis to determine which design alternatives provide the best channel margin!”
Please register here!