Järjestämme maksuttoman Lunch & Learn-tapahtuman Helsingissä keskiviikkona 17.4.2024. Tapahtuman aiheina on FPGA and ASIC development ja AI-Infused Electronic Systems Design, Design Verification for Power Integrity and DDRx design. Ilmoittaudu heti osoitteeseen toimisto@dsys.fi, kuitenkin viimeistään 2.4.2024 mennessä! Tapahtuma pidetään klo 9.30 – 15.00 Lapland Hotels Bulevardissa Helsingissä (Bulevardi 28) ja se on englanninkielinen. Tapahtuma sisältää myös lounaan ja kahvit. Tervetuloa kuulemaan alan uusimmat trendit ja tapaamaan meitä ja Siemensin edustajia! Alla vielä tarkempi ohjelma:
The tools and methodologies are changing. We arrange a free seminar focusing in two main topics:
10:00-12:00 FPGA and ASIC development, Faïçal Chtourou, Field Application Engineer specializing in Design and verification tools, Siemens Digital Industries Software
13:00-15:00 AI-Infused Electronic Systems Design, Design Verification for Power Integrity and DDRx design
Olivier Arnaud, Application Engineer Consultant, Siemens Digital Industries Software
Coffee and refreshments are served in the morning before the session (arrival 9:45 recommended) and during breaks. The lunch break is 12:00-13:00. The lunch includes in the event.
See more detailed abstracts below.
10.00-12:00 FPGA and ASIC development
Advanced FPGA verification overview
“This presentation provides a comprehensive overview of Siemens’ EDA portfolio technologies for FPGA and ASIC development. The focus of the presentation is on the various aspects of verification, including UVM, formal design tool solutions, and Verification IP”
Navigating the Modelsim to Questa Upgrade
By upgrading to Questa, users can unlock a host of new possibilities and benefits, including advanced simulations and enhanced debugging features. This presentation provides a concise overview of the upgrade journey, highlighting the advantages of transitioning from Modelsim to Questa.
Maximizing Early Bug Detection with Questa Design Solution in CI flow
This presentation focuses on empowering designers to enhance the quality of their code deliveries without the hassle of creating testbenches and conducting tests for every block. Questa Design Solutions aims to assist designers in swiftly identifying issues, ensuring code repository stability, and improving the quality of deliveries to other teams. By integrating these tools into a continuous integration flow, automatic and regular code checks can be enabled, resulting in improved efficiency and greater schedule predictability through easily understandable metrics.
13:00-15:00 PCB Layout design and verification
AI-Infused Electronic Systems Design
Introducing the Siemens EDA PCB division upcoming approaches to leverage AI to reduce design time and optimize product performance.
Full Design Verification HyperLynx product suite
Focus on Power Integrity and DDRx design.